1. Field of the Invention
The present invention relates generally to improvements in error detection circuits and, more particularly, pertains to a new and improved error detection system which provides real-time error detection on a continuous stream of digital data.
2. Description of the Prior Art
In the field of digital data error detection, parity error checking schemes are well known and widely practiced. However, such parity checking schemes largely require the use of an additional parity bit being added to a string of "1" and "0" bits. Traditionally, the one bits are counted in a particular length or string of bits which may make up a segment or computer word. If the odd parity system is being utilized, then the number of one bits in every computer word must be odd. If the particular coding of a particular computer word provides an even number of one bits, a binary one parity bit is added. If the particular coding of a particular computer word provides an odd number of one bits, then an 0 parity bit is added.
As can be seen, this procedure requires the counting of the one bits and circuitry to generate the appropriate parity bit at the transmitting end. At the receiving end, again, circuitry must be provided which counts the number of one bits. In addition, circuitry which determines whether the count is odd or even, and circuitry to generate an error condition, if the count is even, must be provided. The same is true if the even parity check is utilized. The odd parity check system is the most widely used, however.
Because of the requirement that a parity bit must be added to provide the odd and even parity, error detection cannot occur on a real-time basis as the data is actually flowing from one location to another. The present invention does not utilize parity bits. The present invention detects the occurrence of errors in a serial data stream that may be any length on a real-time basis.